The present invention relates to a semiconductor memory. In particular, it relates to a circuit for driving the word lines of a semiconductor memory.
A semiconductor memory comprises a plurality of word lines and bit lines that are arrayed in vertical and lateral directions, with memory cells being arrayed at each of the intersecting points. In a static memory, memory cells are usually constructed in the form of a flip-flop circuit. In the metal-oxide semiconductor (MOS)-type memory cell, a pair of signal input/output terminals of the flip-flop circuit are connected to a pair of bit lines via transfer gates (MOS transistors), and the gate electrode wirings of the MOS transistors serve as word lines. The gate electrode wirings are usually formed from polycrystalline silicon, which has a relatively large resistance and creates a static capacitance relative to the substrate to establish a large time constant. If the word line has a large time constant as determined by the product of the resistance and the capacitance, the potential of a word line remote from the selected word driver cannot immediately respond to a change in the output of the selected word driver from a low level to a high level,--i.e., operation is delayed.